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ISL89410, ISL89411, ISL89412
Data Sheet October 17, 2008 FN6798.0
High Speed, Dual Channel Power MOSFET Drivers
The ISL89410, ISL89411, ISL89412 ICs are similar to the EL7202, EL7212, EL7222 series but with greater VDD ratings. These are very high speed matched dual drivers capable of delivering peak currents of 2.0A into highly capacitive loads. The high speed performance is achieved by means of a proprietary "Turbo-Driver" circuit that speeds up input stages by tapping the wider voltage swing at the output. Improved speed and drive capability are enhanced by matched rise and fall delay times. These matched delays maintain the integrity of input-to-output pulse-widths to reduce timing errors and clock skew problems. This improved performance is accompanied by a 10-fold reduction in supply currents over bipolar drivers, yet without the delay time problems commonly associated with CMOS devices. Dynamic switching losses are minimized with non-overlapped drive techniques.
Features
* Industry Standard Driver Replacement * Improved Response Times * Matched Rise and Fall Times * Reduced Clock Skew * Low Output Impedance * Low Input Capacitance * High Noise Immunity * Improved Clocking Rate * Low Supply Current * Wide Operating Voltage Range * Pb-Free Available (RoHS compliant)
Applications
* Clock/line Drivers * CCD Drivers * Ultra-Sound Transducer Drivers
Pinouts
ISL89411 (8 LD PDIP, SOIC) TOP VIEW
NC INA GND INB 1 2 3 4 8 7 6 5 NC OUTA V+ OUTB NC INA GND INB
ISL89410 (8 LD PDIP, SOIC) TOP VIEW
1 2 3 4 8 7 6 5 NC OUTA V+ OUTB
* Power MOSFET Drivers * Switch Mode Power Supplies * Class D Switching Amplifiers * Ultrasonic and RF Generators * Pulsed Circuits
INVERTING DRIVERS
NON-INVERTING DRIVERS
Pin Descriptions
SYMBOL PIN DESCRIPTIONS Power voltage from 4.5V to 18V. Power voltage return Logic inputs. Non-inverted ouput for ISL89410. Inverted output for ISL89411 and ISL89412. Non-inverted output for ISL89410 and ISL89412. Inverted output for ISL89411. These pins must be left unconnected. V+ GND INA, INB
ISL89412 (8 LD PDIP, SOIC) TOP VIEW
NC INA GND INB 1 2 3 4 8 7 6 5 NC OUTA v+ OUTB
OUTA OUTA OUTB OUTB NC
COMPLEMENTARY DRIVERS Manufactured under U.S. Patent Nos. 5,334,883, #5,341,047
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2008. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL89410, ISL89411, ISL89412 Ordering Information
PART NUMBER ISL89410IP ISL89410IBZ (Note) ISL89410IBZ-T13* (Note) ISL89411IP ISL89411IPZ (Note) ISL89411IBZ (Note) ISL89411IBZ-T13* (Note) ISL89412IP ISL89412IBZ (Note) ISL89412IBZ-T13* (Note) PART MARKING ISL 89410IP 89410 IBZ 89410 IBZ ISL 89411IP ISL 89411IPZ 89411 IBZ 89411 IBZ ISL 89412IP 89412 IBZ 89412 IBZ TEMP. RANGE (C) -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 8 Ld PDIP 8 Ld SOIC (Pb-free) 8 Ld SOIC (Tape and Reel) (Pb-free) 8 Ld PDIP 8 Ld PDIP** (Pb-free) 8 Ld SOIC (Pb-free) 8 Ld SOIC (Tape and Reel) (Pb-free) 8 Ld PDIP 8 Ld SOIC (Pb-free) 8 Ld SOIC (Tape and Reel) (Pb-free) PACKAGE PKG. DWG. # MDP0031 MDP0027 MDP0027 MDP0031 MDP0031 MDP0027 MDP0027 MDP0031 MDP0027 MDP0027
*Please refer to TB347 for details on reel specifications. **Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
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FN6798.0 October 17, 2008
ISL89410, ISL89411, ISL89412
Absolute Maximum Ratings
Supply (V+ to GND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.0V Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V above V+ Combined Peak Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . .4A
Thermal Information
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +125C Power Dissipation 8 Ld SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .570mW 8 Ld PDIP* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1050mW Storage Temperature Range . . . . . . . . . . . . . . . . . .-65C to +150C Ambient Operating Temperature . . . . . . . . . . . . . . . .-40C to +85C Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
Maximum Recommended Operating Conditions
Recommended Operating V+ Range. . . . . . . . . . . . . . 4.5V to 18.0V Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to V+
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
DC Electrical Specifications
TA = +25C, V = 18V unless otherwise specified; Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested.
PARAMETER INPUT VIH IIH VIL IIL VHVS OUTPUT ROH ROL IPK IDC POWER SUPPLY IS
DESCRIPTION
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Logic "1" Input Voltage Logic "1" Input Current Logic "0" Input Voltage Logic "0" Input Current Input Hysteresis @0V @V+
2.4 0.1 10 0.8 0.1 0.3 10
V A V A V A A mA
Pull-Up Resistance Pull-Down Resistance Peak Output Current
IOUT = -100mA IOUT = +100mA Source Sink
3 4 2 2 100
6 6
Continuous Output Current
Source/Sink
Power Supply Current
Inputs High/ISL89410 Inputs High/ISL89411 Inputs High/ISL89412
4.5 1 2.5 4.5
7.5 2.5 5.0 18
mA mA mA V
VS
Operating Voltage TA = +25C, V = 18V unless otherwise specified. DESCRIPTION TEST CONDITIONS
AC Electrical Specifications
PARAMETER SWITCHING CHARACTERISTICS tR
MIN
TYP
MAX
UNITS
Rise Time (Note 1)
CL = 500pF CL = 1000pF
7.5 10 10 13 18 20 20 25 25 20
ns ns ns ns ns ns
tF
Fall Time (Note 1)
CL = 500pF CL = 1000pF
tD1 tD2 NOTE:
Turn-On Delay Time (Note 1) Turn-Off Delay Time (Note 1)
See "Timing Table" on page 4 See"Timing Table" on page 4
1. All AC Electrical Specifications are established by characterization and are not production tested.
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FN6798.0 October 17, 2008
ISL89410, ISL89411, ISL89412 Timing Table
5V INPUT 2.5V 0 90% INVERTED OUTPUT 10%
90% NON-INVERTED OUTPUT 10% tD1 tF tR tD2 tR tF
Standard Test Configuration
V+ 4 6 4.7F TAN+ 7 OUTPUT 1000pF
2 INPUT
3
Simplified Schematic
V+
+ INPUT + INPUT BUFFER REFERENCE AND LEVEL SHIFTER INVERTING BUFFER WITH HYSTERESIS 2ND INVERTING BUFFER SUPER INVERTER VREF OUTPUT
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FN6798.0 October 17, 2008
ISL89410, ISL89411, ISL89412 Typical Performance Curves
FIGURE 1. MAX POWER/DERATING CURVES
FIGURE 2. SWITCH THRESHOLD vs SUPPLY VOLTAGE
FIGURE 3. INPUT CURRENT vs VOLTAGE
FIGURE 4. PEAK DRIVE vs SUPPLY VOLTAGE
ISL89410
ISL89411
ISL89412
FIGURE 5. QUIESCENT SUPPLY CURRENT
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FN6798.0 October 17, 2008
ISL89410, ISL89411, ISL89412 Typical Performance Curves
(Continued)
FIGURE 6. "ON" RESISTANCE vs SUPPLY VOLTAGE
FIGURE 7. AVERAGE SUPPLY CURRENT vs VOLTAGE AND FREQUENCY
FIGURE 8. AVERAGE SUPPLY CURRENT vs CAPACITIVE LOAD
FIGURE 9. RISE/FALL TIME vs LOAD
FIGURE 10. RISE/FALL TIME vs SUPPLY VOLTAGE
FIGURE 11. PROPAGATION DELAY vs SUPPLY VOLTAGE
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FN6798.0 October 17, 2008
ISL89410, ISL89411, ISL89412 Typical Performance Curves
(Continued)
FIGURE 12. RISE/FALL TIME vs TEMPERATURE
FIGURE 13. DELAY vs TEMPERATURE
ISL89411 Macro Model
**** ISL89411 Model ****
* input * | gnd * | | Vsupply * | | | Vout .subckt M89411 2 3 6 7 V1 12 3 1.6 R1 13 15 1k R2 14 15 5k R5 11 12 100 C1 15 3 43.3 pF D1 14 13 dmod X1 13 11 2 3 comp1 X2 16 12 15 3 comp1 sp 6 7 16 3 spmod sn 7 3 16 3 snmod g1 11 0 13 0 938 .model dmod d .model spmod vswitch ron3 roff2meg von1 voff1.5 .model snmod vswitch ron4 roff2meg von3 voff2 .ends M89411 7
FN6798.0 October 17, 2008
ISL89410, ISL89411, ISL89412
.subckt comp1 out inp inm vss e1 out vss table { (v(inp) v(inm))* 5000} (0,0) (3.2,3.2) Rout out vss 10meg Rinp inp vss 10meg Rinm inm vss 10meg .ends comp1
V+
Cq
PARASITIC LEAD INDUCTANCE
Application Guidelines
It is important to minimize inductance to the power FET by keeping the output drive current loop as short as possible. Also, the decoupling capacitor, Cq, should be a high quality ceramic capacitor with a Q that should be a least 10x the gate Q of the power FET. A ground plane under this circuit is also recommended.
V+ Cq SHOULD BE AS CLOSE AS POSSIBLE TO THE V+ AND GND PINS Cq
GND
FIGURE 15. SUGGESTED CONFIGURATION FOR DRIVING INDUCTIVE LOADS
Where high supply voltage operation is required (15V to 18V), input signals with a minimum of 3.3V input drive is suggested and a minimum rise/fall time of 100ns. This is recommended to minimize the internal bias current power dissipation. Excessive power dissipation in the driver can result when driving highly capacitive FET gates at high frequencies. These gate power losses are defined by Equation 1:
P = 2 * Q C * V gs * f SW (EQ. 1)
LOOP AS SHORT AS POSSIBLE GND
where: P = Power Qc = Charge of the Power FET at Vgs Vgs = Gate drive voltage (V+) fSW = switching Frequency Adding a gate resistor to the output of the driver will transfer some of the driver dissipation to the resistor. Another possible solution is to lower the gate driver voltage which also lowers Qc.
FIGURE 14. RECOMMENDED LAYOUT METHODS
In applications where it is difficult to place the driver very close to the power FET (which may result with excessive parasitic inductance), it then may be necessary to add an external gate resistor to dampen the inductive ring. If this resistor must be too large in value to be effective, then as an alternative, Schottky diodes can be added to clamp the ring voltage to V+ or GND.
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FN6798.0 October 17, 2008
ISL89410, ISL89411, ISL89412 Small Outline Package Family (SO)
A D N (N/2)+1 h X 45
A E E1 PIN #1 I.D. MARK c SEE DETAIL Au
1 B
(N/2) L1
0.010 M C A B e C H A2 GAUGE PLANE A1 0.004 C 0.010 M C A B b DETAIL X
SEATING PLANE L
0.010
4x
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO) INCHES SYMBOL A A1 A2 b c D E E1 e L L1 h N NOTES: 1. Plastic or metal protrusions of 0.006" maximum per side are not included. 2. Plastic interlead protrusions of 0.010" maximum per side are not included. 3. Dimensions "D" and "E1" are measured at Datum Plane "H". 4. Dimensioning and tolerancing per ASME Y14.5M-1994 SO-8 0.068 0.006 0.057 0.017 0.009 0.193 0.236 0.154 0.050 0.025 0.041 0.013 8 SO-14 0.068 0.006 0.057 0.017 0.009 0.341 0.236 0.154 0.050 0.025 0.041 0.013 14 SO16 (0.150") 0.068 0.006 0.057 0.017 0.009 0.390 0.236 0.154 0.050 0.025 0.041 0.013 16 SO16 (0.300") (SOL-16) 0.104 0.007 0.092 0.017 0.011 0.406 0.406 0.295 0.050 0.030 0.056 0.020 16 SO20 (SOL-20) 0.104 0.007 0.092 0.017 0.011 0.504 0.406 0.295 0.050 0.030 0.056 0.020 20 SO24 (SOL-24) 0.104 0.007 0.092 0.017 0.011 0.606 0.406 0.295 0.050 0.030 0.056 0.020 24 SO28 (SOL-28) 0.104 0.007 0.092 0.017 0.011 0.704 0.406 0.295 0.050 0.030 0.056 0.020 28 TOLERANCE MAX 0.003 0.002 0.003 0.001 0.004 0.008 0.004 Basic 0.009 Basic Reference Reference NOTES 1, 3 2, 3 Rev. M 2/07
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FN6798.0 October 17, 2008
ISL89410, ISL89411, ISL89412 Plastic Dual-In-Line Packages (PDIP)
D E N PIN #1 INDEX
SEATING PLANE L e b
A2
A c
E1
A1 NOTE 5
eA eB
1
2 b2
N/2
MDP0031
PLASTIC DUAL-IN-LINE PACKAGE INCHES SYMBOL A A1 A2 b b2 c D E E1 e eA eB L N NOTES: 1. Plastic or metal protrusions of 0.010" maximum per side are not included. 2. Plastic interlead protrusions of 0.010" maximum per side are not included. 3. Dimensions E and eA are measured with the leads constrained perpendicular to the seating plane. 4. Dimension eB is measured with the lead tips unconstrained. 5. 8 and 16 lead packages have half end-leads as shown. PDIP8 0.210 0.015 0.130 0.018 0.060 0.010 0.375 0.310 0.250 0.100 0.300 0.345 0.125 8 PDIP14 0.210 0.015 0.130 0.018 0.060 0.010 0.750 0.310 0.250 0.100 0.300 0.345 0.125 14 PDIP16 0.210 0.015 0.130 0.018 0.060 0.010 0.750 0.310 0.250 0.100 0.300 0.345 0.125 16 PDIP18 0.210 0.015 0.130 0.018 0.060 0.010 0.890 0.310 0.250 0.100 0.300 0.345 0.125 18 PDIP20 0.210 0.015 0.130 0.018 0.060 0.010 1.020 0.310 0.250 0.100 0.300 0.345 0.125 20 TOLERANCE MAX MIN 0.005 0.002 +0.010/-0.015 +0.004/-0.002 0.010 +0.015/-0.010 0.005 Basic Basic 0.025 0.010 Reference Rev. C 2/07 2 1 NOTES
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 10
FN6798.0 October 17, 2008

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